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  Publications/ Presentations: 
 

  • "Multi stage pipelined DCTQ processor for high throughput video compression",  International Conference on Electrical, Electronics and Computer Science(ICEECS-2012), Chandigarh, 25 Nov. 2012, pp. 52-56, ISBN: 978-93-81693-68-7.
  • "A Verilog Implimentation of Pipelined Scaling-Free Vectoring Mode CORDIC Processor", 17th International Symposium on VLSI Design and Test (VDAT-2013), MNIT Jaipur.
  • Nishant Kumar, Ekta Aggrawal, Ashish Gambhir, "Implementation of Sayeh Processor in VHDL using Perl Assembler", International Journal of Electrical, Electronics and Computer Research and Development (IJEECRD), Vol 1, Issue 1, Oct 2014, ISSN 2394-3246.
  • Ashish Gambhir, Kavita Khare, "A Verilog Implementation of IEEE 754 Standard Compliant Conventional CORDIC Processor", European Journal of Science and Research, SCI Indexed Journal(Under Review)